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CA5260, CA5260A
Data Sheet December 23, 2005 FN1929.6
3MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output
The CA5260A and CA5260 are integrated-circuit operational amplifiers that combine the advantage of both CMOS and bipolar transistors on a monolithic chip. The CA5260 series circuits are dual versions of the popular CA5160 series. They are designed and guaranteed to operate in microprocessor or logic systems that use +5V supplies. Gate-protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very-high-input impedance, very-low-input current, and exceptional speed performance. The use of PMOS field-effect transistors in the input stage results in common-mode input-voltage capability down to 0.5V below the negative-supply terminal, an important attribute in single-supply applications. A complementary-symmetry MOS (CMOS) transistor-pair, capable of swinging the output voltage to within 10mV of either supply-voltage terminal (at very high values of load impedance), is employed as the output circuit. The CA5260 Series circuits operate at supply voltages ranging from 4.5V to 16V, or 2.25V to 8V when using split supplies. The CA5260, CA5260A have guaranteed specifications for 5V operation over the full military temperature range of -55C to 125C.
Features
* MOSFET Input Stage provides - Very High ZI . . . . . . . . . . . . . 1.5T (1.5 x 1012) (Typ) - Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation 2pA (Typ) at 5V Operation * Ideal for Single Supply Applications * Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can be Swung 0.5V Below Negative Supply Rail * CMOS Output Stage Permits Signal Swing to Either (or Both) Supply Rails * CA5260A, CA5260 Have Full Military Temperature Range Guaranteed Specifications for V+ = 5V * CA5260A, CA5260 are Guaranteed to Operate Down to 4.5V for AOL * Fully Guaranteed to Operate from -55C to 125C at V+ = 5V, V- = GND * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Ground Referenced Single Supply Amplifiers * Fast Sample-Hold Amplifiers * Long Duration Timers/Monostables * Ideal Interface with Digital CMOS * High Input Impedance Wideband Amplifiers * Voltage Followers (e.g., Follower for Single Supply D/A Converter) * Voltage Regulators (Permits Control of Output Voltage Down to 0V) * Wien Bridge Oscillators
Pinout
CA5260 (SOIC) TOP VIEW
1 A 2 3 4 + B + 8 7 6 5
OUTPUT (A) INV. INPUT (A) NON INV. INPUT (A) V-
V+ OUTPUT (B) INV. INPUT (B) NON INV. INPUT (B)
-
* Voltage Controlled Oscillators * Photo Diode Sensor Amplifiers * 5V Logic Systems * Microprocessor Interface
-
Ordering Information
PART NUMBER CA5260AM96 CA5260M CA5260MZ (Note) CA5260MZ96 (Note) 5260A 5260 CA5260MZ CA5260MZ PART MARKING TEMP. RANGE (C) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 8 Ld SOIC Tape and Reel 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) PKG. DWG. # M8.15 M8.15 M8.15 M8.15
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-37743 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
CA5260, CA5260A
Absolute Maximum Ratings
Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . 16V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Thermal Information
Thermal Resistance (Typical, Note 2)
JA (C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . 175C Maximum Junction Temperature (Plastic Package) . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (Lead Tips Only)
NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25C, Unless Otherwise Specified TYPICAL VALUES
PARAMETER Input Resistance Input Capacitance Unity Gain Crossover Frequency Slew Rate Transient Response Rise Time Overshoot Settling Time (To <0.1%, VIN = 4VP-P)
SYMBOL RI CI fT SR
TEST CONDITIONS
CA5260 1.5
CA5260A 1.5 4.3 3 5
UNITS T pF MHz V/s s % s
f = 1MHz
4.3 3
VOUT = 2.5VP-P CL = 25pF, RL = 2k (Voltage Follower)
5
tr OS tS
0.09 10
0.09 10 1.8
CL = 25pF, RL = 2k (Voltage Follower)
1.8
Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Current Common Mode Rejection Ratio Common Mode Input Voltage Range Power Supply Rejection Ratio Large Signal Voltage Gain (Note 3)
TA = 25C, V+ = 5V, V- = 0V TEST CONDITIONS VO = 2.5V VO = 2.5V VO = 2.5V VCM = 0 to 1V VCM = 0 to 2.5V VlCR+ VlCRPSRR AOL V+ = 1V; V- = 1V RL = , VO = 0.5 to 4V RL = 10k, VO = 0.5 to 3.6V CA5260 MIN 70 50 2.5 70 105 80 1.75 1.70 TYP 2 1 2 85 55 3 -0.5 84 111 86 2.2 2 MAX 15 10 15 0 MIN 80 50 2.5 75 107 83 1.75 1.70 CA5260A TYP 1.5 1 2 85 55 3 -0.5 84 113 86 2.2 2 MAX 4 10 15 0 UNITS mV pA pA dB dB V V dB dB dB mA mA
SYMBOL VIO IIO II CMRR
Source Current Sink Current
ISOURCE ISINK
VO = 0V VO = 5V
2
FN1929.6 December 23, 2005
CA5260, CA5260A
Electrical Specifications
PARAMETER Output Voltage TA = 25C, V+ = 5V, V- = 0V (Continued) TEST CONDITIONS RL = CA5260 MIN 4.99 RL = 10k 4.4 RL = 2k 3 VO = 0V VO = 2.5V NOTE: 3. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10k. TYP 5 0 4.7 0 3.4 0 1.60 1.80 MAX 0.01 0.01 0.01 2.0 2.25 MIN 4.99 4.4 3 CA5260A TYP 5 0 4.7 0 3.4 0 1.60 1.80 MAX 0.01 0.01 0.01 2.0 2.25 UNITS V V V V V V mA mA
SYMBOL VOM+ VOMVOM+ VOMVOM+ VOM-
Supply Current
ISUPPLY
Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Current Common Mode Rejection Ratio
TA = -55C to 125C, V+ = 5V, V- = 0V TEST CONDITIONS VO = 2.5V VO = 2.5V VO = 2.5V VCM = 0 to 1V VCM = 0 to 2.5V CA5260 MIN 60 50 2.5 V+ = 1V; V- = 1V RL = , VO = 0.5 to 4V RL = 10k, VO = 0.5 to 3.6V 60 70 60 1.3 1.2 4.99 RL = 10k 4.2 RL = 2k 2.5 VO = 0V VO = 2.5V TYP 3 1 2 78 60 3 -0.5 65 78 65 1.6 1.4 5 0 4.4 0 2.7 0 1.65 1.95 MAX 20 10 15 0 0.01 0.01 0.01 2.2 2.35 MIN 65 50 2.5 62 70 60 1.3 1.2 4.99 4.2 2.5 CA5260A TYP 2 1 2 78 60 3 -0.5 65 78 65 1.6 1.4 5 0 4.4 0 2.7 0 1.65 1.95 MAX 15 10 15 0 0.01 0.01 0.01 2.2 2.35 UNITS mV nA nA dB dB V V dB dB dB mA mA V V V V V V mA mA
SYMBOL VIO IIO II CMRR
Common Mode Input Voltage Range Power Supply Rejection Ratio Large Signal Voltage Gain (Note 4)
VlCR+ VlCRPSRR AOL
Source Current Sink Current Output Voltage
ISOURCE ISINK VOM+ VOMVOM+ VOMVOM+ VOM-
VO = 0V VO = 5V RL =
Supply Current
ISUPPLY
NOTE: 4. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10k.
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FN1929.6 December 23, 2005
CA5260, CA5260A
Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Current Large Signal Voltage Gain Each Amplifier at TA = 25C, V+ = 15V, V- = 0V, Unless Otherwise Specified TEST CONDITIONS VS = 7.5 VS = 7.5 VS = 7.5 VO = 10VP-P, RL = 10k CA5260 MIN 50 94 70 10 VS = 7.5 RL = 10k RL = 11 14.99 VO = 7.5V 12 12 VO (Amp A) = 7.5V VO (Amp B) = 7.5V VO (Amp A) = 0V VO (Amp B) = 0V VO (Amp A) = 0V VO (Amp B) = 7.5V Input Offset Voltage Temperature Drift Crosstalk VIO/T f = 1kHz TYP 6 0.5 5 320 110 90 -0.5 to 12 32 13.3 0.002 15 0 22 20 9 1.2 5 8 120 MAX 15 30 50 0 320 0.01 0.01 45 45 16.5 4 9.5 MIN 50 94 80 10 11 14.99 12 12 CA5260A TYP 2 0.5 5 320 110 95 -0.5 to 12 32 13.3 0.002 15 0 22 20 9 1.2 5 6 120 MAX 5 20 30 0 150 0.01 0.01 45 45 16.5 4 9.5 UNITS mV pA pA kV/V dB dB V V/V V V V V mA mA mA mA mA V/C dB
SYMBOL VIO IIO II AOL
Common Mode Rejection Ratio Common Mode Input Voltage Range Power Supply Rejection Ratio, VIO/ V Maximum Output Voltage
CMRR VlCR PSRR VOM+ VOMVOM+ VOM-
Maximum Output Current
IOM+ (Source) IOM- (Sink)
Total Supply Current, RL =
I+
4
FN1929.6 December 23, 2005
CA5260, CA5260A Schematic Diagram
V+ 8 AMPLIFIER A AMPLIFIER B
Q11
Q10 D2
Q6
Q7
Q9
Q21 Q23 D6
Q20 Q24
Q25 D7
D3
D1 Q12 Q14 R6 200K C3 Q13 R3 1K Q3 R1 1K 3 +IN Q1 Q2
D4
R5 2K C1 30pF Q5 Q8
Q22
R12 2K C2 30pF
D5 Q16 Q15
D8 Q26 R10 Q27 1K Q17 R8 1K 5 +IN R14 300 Q28 C4 R13 200K
R4 1K
R11 1K
Q19 Q18 R9 1K
R7 300K
Q4 R2 1K 2 -IN 1 7 6 -IN
4 V-
OUT
5
FN1929.6 December 23, 2005
CA5260, CA5260A Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 6
FN1929.6 December 23, 2005

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